Typical CMOS device/process options
I received an inquiry on how to reduce leakage. I will cover how to do so in a future article. However, before I do, let’s go over some process options that effect leakage. Core Devices Typically,...
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Minimizing leakage for high-performance CMOS circuits
I was asked a question on how to reduce leakage for digital circuits. I started by detailing process options that effect leakage, each effective both leakage and circuit performance. In this article, I...
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You want latches? We got latches | Flip-Flop Design
I received a request to go through the design of a flip-flop. Every flip-flop I have designed has been a master-slave D flip-flop, built out of two D latches. I’ll start with a basic CMOS latch and go...
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Non-Radix-2 FFT in Cadence/Ocean/Skill/Spectre | Using Cadence IPC to talk to...
Introduction I had been working on a pulse-width-modulation (PWM) design. It was a pseudo-digital implementation, in that the output was clocked by a high-speed clock. The actual switching rate was...
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Median vs Mean
I’ve been doing some statistical measurements lately (more to follow). It occurs to me that while most people measure the mean of a set of measurements, the median is more useful. If the distribution...
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